1. Field of the Invention
The invention generally relates to memory devices and, more particularly, to detecting the phase difference between a clock signal and a data strobe signal.
2. Description of the Related Art
In many memory designs there is often more than one timing signal and generally these timing signals may be skewed. In general, skew refers to the difference in timing between two timing signals, e.g., the time from the leading edge of the first timing signal to the leading edge of the second timing signal. In some designs, one timing signal may be allowed to be skewed to another by a predetermined allowance. For example, in current double data rate DDR dynamic random access memory (DRAM) designs, the phase relationship of a data strobe signal (DQS) and a clock signal (CLK) may be skewed by up to +/−25%. In some memory designs, certain logic within the memory may be timed to the CLK signal, or within the CLK domain, while other logic within the memory may be timed to the DQS signal, or within the DQS domain.
In conventional DRAM designs, internal synchronization was done by adjusting the internal timings to accommodate the worst-case DQS−CLK skew condition. An example of this approach is shown in FIG. 1. Three potential DQS signals are shown, DQS @ tDQSSnom, DQS @ tDQSSmin and DQS @ tDQSSmax, representing the nominal DQS timing and the two worst-case DQS timings, when DQS leads CLK by 25% and when DQS lags CLK by 25%. The memory's internal timing must be able to operate over this entire range of CLK/DQS timing, which is becoming more difficult as clock speed increase. In this example, the timing of the DQS signal may be closely synchronized with CLK (DQS @ tDQSSnom) or may lead the CLK by up to 25% (DQS @ tDQSSmin) or may lag the CLK by up to 25% (DQS @ tDQSSmax), providing a CLK−DQS skew range as indicated.
In conventional DRAM designs, internal timing had to be set to compensate for this wide range of timing differences, having to operate over a range of from −25% to +25%. The prior designs had to assume a worst-case phase difference and deal with that difference, perhaps by having tighter internal timings. As memory clock speeds increase, it becomes more difficult to compensate for these timing differences and internal signals derived from these clock and data strobe signals may need to be closer aligned to the clock to prevent errors from occurring. Rather than accommodate the worst case timing, it would be beneficial to adjust internal timing signals based on the actual phase difference between the DQS and CLK signals. However, in conventional designs, no attempt has been made to detect this phase difference.
Therefore, what is needed are methods and apparatus for detecting, at a memory device, the phase difference between a clock signal (CLK) and a data strobe signal (DQS) and using this detected difference to adjust signal timing.